By Topic

A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-µm digital CMOS process

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Chun-Cheng Liu ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Yi-Ting Huang ; Guan-Ying Huang ; Soon-Jyh Chang
more authors

This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-mum 1P5M digital CMOS technology, the ADC only occupies 0.032 mm2 active area.

Published in:

VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on

Date of Conference:

28-30 April 2009