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Exploiting advanced fault localization methods for yield & reliability learning on SoCs

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1 Author(s)
Appello, D. ; STMicroelectronics srl, Italy

This paper proposes advances on fault localization methods suiting the learning of yield and reliability in VLSI CMOS technologies. Industrial methodologies and tools will be discussed and the experimental results obtained through their implementation will be presented.

Published in:

VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on

Date of Conference:

28-30 April 2009