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Leakage reduction, variation compensation using partition-based tunable body-biasing techniques

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4 Author(s)
Po-Yuan Chen ; Dept. of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300 ; Chiao-Chen Fang ; TingTing Hwang ; Hsi-Pin Ma

As fabrication technology progresses, several new challenges follow. Among them, the most noticeable two are process variations and leakage current of the circuit. To tackle these two problems, an effective way is to use body biasing technique. In substance, using RBB technique can minimize leakage current but increase the delay of a gate. FBB technique decreases the delay but increases leakage current. In previous works, a single body biasing is applied to whole circuit. In a slow circuit, since the FBB is applied to whole circuit, the leakage current increases dramatically. In a fast circuit, RBB is applied to decrease the leakage current. However, without violating the timing specification, the value of body biasing is restricted by the critical paths, and the saving of leakage current is limited. In this paper, we propose a design flow to partition the circuit into subcircuits so that each subcircuit can be applied its individual RBB or FBB to reduce the leakage current and cope with process variations. In the experimental result, our method is able to save leakage current from 41% to 46% as compared with design without body biasing technique. Under process variations, our method can save 40% to 49% leakage on fast circuits and 15% to 32% on slow circuits.

Published in:

VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on

Date of Conference:

28-30 April 2009