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This paper describes a 10-bit 40 MS/s low power pipelined analog-to-digital converter (ADC). A novel pre-charged fast power-on switched operational amplifier is used to lower power consumption of the pipelined ADC to 13.82 mW. The ADC is designed in a 1.8 V 1P6M 0.18-mum CMOS process. Simulation results indicate that the ADC exhibits Spurious Free Dynamic Range (SFDR) of 74.19 dB and Signal to Noise and Distortion Ratio (SNDR) of 60.25 dB when a 19.02 MHz sinusoidal signal is feed-in.