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A 10-bit 40MS/s pipelined ADC with pre-charged switched operational amplifier

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2 Author(s)
Qi Wei ; Dept. of Electron. Eng., Tsinghua Univ., Beijing, China ; Huazhong Yang

This paper describes a 10-bit 40 MS/s low power pipelined analog-to-digital converter (ADC). A novel pre-charged fast power-on switched operational amplifier is used to lower power consumption of the pipelined ADC to 13.82 mW. The ADC is designed in a 1.8 V 1P6M 0.18-mum CMOS process. Simulation results indicate that the ADC exhibits Spurious Free Dynamic Range (SFDR) of 74.19 dB and Signal to Noise and Distortion Ratio (SNDR) of 60.25 dB when a 19.02 MHz sinusoidal signal is feed-in.

Published in:

Consumer Electronics, 2009. ISCE '09. IEEE 13th International Symposium on

Date of Conference:

25-28 May 2009