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Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers

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2 Author(s)
Lan-Da Van ; Dept. of Comput. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Jin-Hao Tu

In this paper, we propose a pipelined reconfigurable fixed-width Baugh-Wooley multiplier design framework that provides four configuration modes (CMs): n ?? n fixed-width multiplier, two n/2 ?? n/2 fixed-width multipliers, n/2 ?? n/2 full-precision multiplier, and two n/A ?? n/A full-precision multipliers. Furthermore, low-power schemes including gated clock and zero input techniques are employed to achieve the power-efficient pipelined reconfigurable design. The presented power-efficient pipelined reconfigurable fixed-width multiplier design not only generates a family of widely used multipliers but also leads to 10.59, 21.7, 28.84, and 31.58 percent power saving, on average, for n = 8,16,24, and 32, respectively, compared with that of the pipelined reconfigurable fixed-width multiplier without using the low-power schemes. On the other hand, compared with non-reconfigurable pipelined multiplier, we can save 0.81, 12.46, 17.93, and 23.2 percent power consumption, respectively, for n = 8,16,24, and 32.

Published in:

Computers, IEEE Transactions on  (Volume:58 ,  Issue: 10 )