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Exploiting Inherent Parallelisms for Accelerating Linear Hough Transform

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3 Author(s)
Sathyanarayana, S.S. ; Center for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore, Singapore ; Satzoda, R.K. ; Srikanthan, T.

Accelerating Hough transform in hardware has been of interest due its popularity in real-time capable image processing applications. In most existing linear Hough transform architectures, an m times medge map is serially read for processing, resulting in a total computation time of at least m2 cycles. In this paper, we propose a novel parallel Hough transform computation method called the Additive Hough transform (AHT), wherein the image is divided using a k times k grid to reduce the total computation time by a factor of k2. We have also proposed an efficient implementation of the AHT consisting of a look-up table (LUT) and two-operand adder arrays for every angle. Techniques to condense the LUT size have also been proposed to further reduce area utilization by as much as 50%. Our investigations based on employing an 8 times 8 grid shows a 1000 times speedup compared to existing architectures for a range of image sizes. Area-time trade-off analysis has been presented to demonstrate that the area-time product of the proposed AHT-based implementation is at least 43% lower than other implementations reported in the literature. We have also included and characterized a hierarchical addition step in order to generate a global accumulation space equivalent to that of the conventional HT. It is shown that the proposed implementation with the hierarchical addition step remains superior to other methods in terms of both performance and area-time product metrics. Finally, we show that the proposed solution is equally efficient when applied on rectangular images.

Published in:

Image Processing, IEEE Transactions on  (Volume:18 ,  Issue: 10 )