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Scanning Auger of a specific via interface in an integrated circuit using a novel focused ion beam sample preparation technique

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4 Author(s)
Liu, W. ; Technology Solutions Organization, Physical Analysis Lab, Freescale Semiconductor Inc., Chandler, Arizona 85224 ; Ramirez, H. ; Schauer, S. ; Theodore, N.D.

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Auger depth profile analysis can be impeded by surface roughening during ion sputtering. This is especially noticeable when analyzing semiconductor devices because of the variety of materials that are susceptible to roughening, as well as the importance of very thin interfaces. A novel technique is presented in this article, which combines scanning Auger analysis with focused ion beam (FIB) thinning for analysis of single via interfacial structures in integrated circuit devices. After a failing structure was identified by electrical fault isolation techniques, FIB was used to remove all of the materials from the top of the device. The materials include polyimide, passivation, metal layers, and dielectric layers. The layers were removed to a level approximately 100 Å above the via interface under a tungsten plug. A scanning Auger instrument was then used for Auger depth profiling of the single via. A thin oxidized interface was observed between Ti/TiN glue layer and antireflection coating (ARC) TiN and was identified as the cause of the via failure. It would have been impossible for conventional sputter depth profiling to detect this thin oxidized layer buried under several layers of materials. Further investigation showed that the interfacial oxide is caused by backsputtering of ARC TiN during via etch and rf sputtering before Ti/TiN glue deposition.

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Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films  (Volume:27 ,  Issue: 4 )