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Electro-static induced metal breakdown at interlayer dielectric post CMP brush clean process

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15 Author(s)
Lariviere, S. ; Altis Semicond., Corbeil-Essonnes, France ; Picore, F. ; Saez, P.L. ; Baltzinger, J.-L.
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During the introduction of a new product on an already qualified 0.25 mum technical node, wafer functional yields were found lower then expected compare to reference level. Basically, failing chips on TEM were showing an Electro-Static Discharge breakdown crack between two metal 2 lines. Process module partitioning and tool charging analysis pointed out the scrubber used to clean and dry wafers at the post interlayer dielectric chemical mechanical polishing step. Tool design analysis and process parameters experiments have been evaluated according to a new charging monitoring tool. Two alternate solutions have been found and confirmed at the end by functional yield recovery to technical node standard. This paper describes the investigation methodology from the earliest predictive failure analysis to the final manufacturing implemented fix that includes an innovative monitoring scheme.

Published in:

Advanced Semiconductor Manufacturing Conference, 2009. ASMC '09. IEEE/SEMI

Date of Conference:

10-12 May 2009