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Yield analysis of fault-tolerant multichip module systems for massively parallel computing

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2 Author(s)
Sungsoo Kim ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; Lombardi, Fabrizio

This paper presents analytical models for evaluating the overall yield of systems manufactured using fault-tolerant multichip modules (MCMs) for massively parallel computing. In the proposed approaches, we employ a novel Markov model to compute the yield. Unlike a previous method which utilizes a binomial distribution, our scheme can employ intermediate tests. Several strategies for appropriately testing fault-tolerant MCMs have been proposed, but little analytical evaluation has been performed. In this paper, it is shown that an efficient test strategy with a modest level of redundancy may exist to achieve virtually 100% first-pass MCM yield for a particular system. We note that a yield-analysis model employing the LRT (Least Recently Tested) test strategy proposed in this paper may provide a very good figure of merit due to its cost, delivery, number of tests and reliability benefits for today's technology. Extensive parametric results for the analysis are provided to show that our approach can be applied to calculate the overall yield for fault-tolerant MCMs more accurately and efficiently, thereby improving upon the reliability of the entire system

Published in:

Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on

Date of Conference:

18-20 Jan 1995