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Optimal switching networks for WSI architectures with fault tolerant path routing

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2 Author(s)
Liu, T. ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; Lombardi, F.

This paper presents an approach for designing fault-tolerant routers for signal distribution by redundant path routing in wafer scale integration (WSI) architectures. The conditions by which a router can be designed using spare lines (tracks) such that the probability of successfully routing all input lines in the prescribed order and in the presence of faults in switches can be optimized (optimality), are proved using a probabilistic analysis. An algorithm which determines the placement of the switches in the router to satisfy the optimality conditions is presented

Published in:

Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on

Date of Conference:

18-20 Jan 1995