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Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

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8 Author(s)
Claude Ortolland ; Interuniversity Microelectron. Center, Leuven, Belgium ; Yasutoshi Okuno ; Peter Verheyen ; Christoph Kerner
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In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented.

Published in:

IEEE Transactions on Electron Devices  (Volume:56 ,  Issue: 8 )