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Layout Optimization of ESD Protection Diodes for High-Frequency I/Os

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3 Author(s)
Bhatia, K. ; Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA ; Jack, N. ; Rosenbaum, E.

Layout options for CMOS ESD diodes' p-n junction geometry and metal routing are investigated in this paper. Experiments are performed using 90- and 180-nm technologies. Using the figures of merit ICP/C and R ON * C, it is shown that twin-well stripe diodes with nonminimum diffusion width and high-level broadside routing are optimum for gigahertz-frequency I/Os. In addition, the suitability of ESD diodes formed with the isolated P-well/deep N-well diffusions available in triple-well technologies is evaluated for high-speed I/O applications.

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Device and Materials Reliability, IEEE Transactions on  (Volume:9 ,  Issue: 3 )