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Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer

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10 Author(s)
Tetsuro Satoh ; Supercond. Res. Lab., ISTEC, Tsukuba, Japan ; Kenji Hinode ; Shuichi Nagasawa ; Yoshihiro Kitagawa
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We have developed an advanced process for fabricating a next-generation multi-layer Nb integrated circuit structure incorporating a top active layer. In this structure, the passive-transmission-line (PTL) layer is placed between the top active layer and a DC-bias current layer at the bottom. This structure will make it possible to flexibly design active circuits and PTL wiring, and will also enable active circuits to be effectively shielded from magnetic fields generated by a large DC-bias current. Both the DC-bias current layer and the PTL layer are planarized; however, the top active layer is fabricated without planarization. To fabricate this new structure, it was necessary to achieve a better planarization process for junctions formed over underlying Nb patterns. The combined process we developed comprising additional SiO2 deposition and additional mechanical polishing after the standard Caldera planarization process results in superior planarization for junction formation. We obtained excellent characteristics of junctions formed over underlying pattern edges when they were fabricated on surfaces planarized using this new process. Using the process, we fabricated new 10-Nb-layer integrated circuit structures and estimated the characteristics of their circuit elements.

Published in:

IEEE Transactions on Applied Superconductivity  (Volume:19 ,  Issue: 3 )