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ECSTAC: a fast asynchronous microprocessor

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3 Author(s)
Morton, S.V. ; Southbank Univ., London, UK ; Appleton, S.S. ; Liebelt, M.J.

This paper introduces some of the principal design issues encountered in the development of a prototype asynchronous microprocessor using a two-phase communication strategy. These issues include the control of the processor pipeline, register tagging, branch techniques, and the implementation of caches. The arbitration and synchronisation methods employed in the design are discussed, and expected performance figures based on block simulation results are given

Published in:

Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on

Date of Conference:

30-31 May 1995

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