Hot carrier induced interface trap annealing in silicon field effect transistors

Interface traps are created in metal‐oxide‐semiconductor field‐effect transistors when hot carrier stressing is done with the maximum substrate current biasing condition (Vd=6.0 V and Vg=2.9 V). Unlike trapped oxide charge, the interface traps are not annealed by keeping the device at room temperature for 24 h. However, by applying reverse bias with high positive drain voltage Vd and negative gate voltage Vg, the hot carrier induced interface traps can be completely annealed out. This is confirmed by both transconductance and charge pumping measurements. There is a direct relationship between the substrate current and annealing of interface states by reverse stressing. The possible mechanism of interface state annealing is discussed.