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Hierarchical gate-level verification of speed-independent circuits

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3 Author(s)
O. Roig ; Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain ; J. Cortadella ; E. Pastor

This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical verification

Published in:

Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on

Date of Conference:

30-31 May 1995