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Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology

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3 Author(s)
M. Kameyama ; Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan ; T. Sekibe ; T. Higuchi

A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod m/sub i/ multiplication can be simply performed by a shift operation. In mod m/sub i/ addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10- mu m CMOS technology.<>

Published in:

Multiple-Valued Logic, 1988., Proceedings of the Eighteenth International Symposium on

Date of Conference:

0-0 1988