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A digital systolic neural network chip (DSNC)

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2 Author(s)
N. Weinberg ; Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel ; R. Ginosar

The DSNC chip implements one neural network layer having 25 fully inter-connected neurons. It is a digital, systolic, pipelined, integer based architecture. The chip is primarily designed for image processing tasks devised upon the basic backpropagation neural-network algorithm. Forward processing as well as learning are supported and carried out in parallel with each other. A network built using this chip can have unlimited number of layers when working in forward mode, and up to three layers if learning is required. The topology of a network is user defined. A chip can handle up to 25 inputs in each input example. Input and output data are nine bits; weights, biases and their updated values are eight bits. A chip can process images of up to 550/spl times/550 pixels in real-time when processing neighborhoods of 25 pixels, and larger images when using smaller neighborhoods. The chip requires about two million transistors and 180 I/O pins.

Published in:

Electrical and Electronics Engineers in Israel, 1995., Eighteenth Convention of

Date of Conference:

7-8 March 1995