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Fast soft error sensitivity characterization technique is essential for the soft error tolerance optimization of modern VLSI circuits. In this paper, an efficient soft error evaluation technique based on syntax analysis and state probability propagating technique is developed, which can automatically analyze the soft error rate of combinational logic circuits and the combinational part of sequential circuits in Verilog synthesized netlist within a few seconds. We implemented the idea in a software tool called HSECT-ANLY, which use Verilog syntax analysis to automate the soft error rate evaluation procedure and state propagating technique to speed up the analyzation process. By using HSECT-ANLY, experiments are carried out on some ISCAS'85 and ISCAS'89 benchmark circuits implemented with TSMC 0.18 mum technology and results are obtained. The result comparison with the traditional test vector propagating technique shows that the introduced method is much faster (2-3 magnitudes speeding up) with some accuracy losses, and be very suitable for the reliability optimization as the sub-algorithm of the optimization algorithms such as genetic algorithms to evaluate the fitness (soft error rate) rapidly.