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A 60-GHz CMOS receiver with an on-chip ADC

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8 Author(s)
Varonen, M. ; TKK Helsinki Univ. of Technol., Espoo, Finland ; Kaltiokallio, M. ; Saari, V. ; Viitala, O.
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A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is -38.5 dBm.

Published in:

Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE

Date of Conference:

7-9 June 2009