By Topic

Elastic relaxation in patterned and implanted strained silicon on insulator

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Baudot, S. ; Equipe mixte CEA-CNRS “Nanophysique et semiconducteurs,” SP2M, INAC, CEA, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France ; Andrieu, F. ; Rieutord, F. ; Eymery, J.

Your organization might have access to this article on the publisher's site. To check, click on this link: 

Mechanical relaxations of strained silicon on insulator (sSOI) nanostructures are studied for the isolation and implantation processes used in transistor technology. Two model systems are quantitatively analyzed by grazing incidence x-ray diffraction: long etched sSOI lines of different widths and bidimensional (2D) sSi samples implanted by As/Xe ions with the same stripe geometry, the gate stack acting as an implantation mask. For sSOI lines, the strain of the initial 2D layer is conserved along the longer direction, i.e., the transport direction. Along the small direction, a large relaxation is observed especially for the smaller widths. This relaxation is almost complete for thicker samples (70 nm), whereas it is much more limited for thinner ones (10 nm). The tuning by etching/size selection of the sSOI initial biaxial stress into uniaxial stress along the transport direction should represent a great advantage for n-metal oxide semiconductor (n-MOS) devices in terms of mobility. Similar relaxation anisotropies have been observed for the implanted samples with 60 nm thickness. In this case, the relaxed small dimension of the area under the gate stack corresponds to the transport direction. This direct source/drain implantation step should therefore damage the performance of partially depleted sSOI n-MOS devices. However these relaxation phenomena should be advantageously used with new integration schemes.

Published in:

Journal of Applied Physics  (Volume:105 ,  Issue: 11 )