By Topic

Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Shaik, I.P. ; Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA ; Bushnell, M.L.

We propose a quadratic 0-1 approach to redesign a circuit in order to test it for excessive delays using a new robust delay-fault Built-In Self Testing (BIST) model. This approach models the problem as a weighted signed graph balancing problem. The algorithm has O(n2 ) complexity, where n is the number of circuit nodes. We drop hardware from false timing paths to lower the delay fault BIST hardware overhead to 17% in large circuits (measured overhead in addition to stuck-fault BIST overhead). Results show that the computation is rapid for the 1985 ISCAS benchmarks

Published in:

VLSI Test Symposium, 1995. Proceedings., 13th IEEE

Date of Conference:

30 Apr-3 May 1995