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Reducing test application time in scan design schemes

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2 Author(s)
Vinnakota, B. ; Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA ; Stessman, N.J.

We present new methods to reduce test times in sequential circuits using scan. The problem of reducing test application time is shown to be computationally intractable. We discuss heuristic techniques to reduce test times. Fault simulation and correlation between test vectors are used to reduce test times, without affecting fault coverage. Our methods can be used to process a test set after test generation is complete. They lead to a substantial reduction in test times

Published in:

VLSI Test Symposium, 1995. Proceedings., 13th IEEE

Date of Conference:

30 Apr-3 May 1995