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Scan testing of micropipelines

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2 Author(s)
O. A. Petlin ; Dept. of Comput. Sci., Manchester Univ., UK ; S. B. Furber

The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor. A method to design and test micropipelines is presented in this paper. The test strategy is based on the scan test technique. It allows the separate testing of all the data processing blocks by scanning the test patterns in and shifting the responses out of the stage registers. The proposed test approach provides for the detection of all single stuck-at and delay faults in the micropipeline. Tests for the combinational processing logic and state holding elements can be derived using standard test generation techniques

Published in:

VLSI Test Symposium, 1995. Proceedings., 13th IEEE

Date of Conference:

30 Apr-3 May 1995