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Verilog-based performance evaluation of a multiprocessor system

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2 Author(s)
Anyanwu, C.D. ; Brunel Univ., Uxbridge, UK ; Jalowiecki, I.P.

We present the outcome of an exercise to model, in Verilog HDL, a non-homogeneous, pyramid-organised, multiprocessor system. The model has been constructed to represent, at varying degrees of detail, the dynamic behaviour of the system and has subsequently been verified and calibrated against components of the realised system. The paper discusses the performance of the model, the type of results available, and the experience gained from the activity

Published in:

Verilog HDL Conference, 1995. Proceedings., 1995 IEEE International

Date of Conference:

27-29 Mar 1995