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An improved output compaction technique for built-in self-test in VLSI circuits

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4 Author(s)
Das, S.R. ; Dept. of Electr. Eng., Ottawa Univ., Ont., Canada ; Ho, H.T. ; Wen-Ben Jone ; Nayak, A.R.

In this paper, we propose a space compression technique for digital circuits for minimizing the storage for the circuits under test while maintaining the fault coverage information. In this technique, a compaction tree is generated based on the circuit under test. The detectable error probability is calculated by using the Boolean Difference Method. The output modification is employed to minimize the number of faulty output data patterns which have the same compressed form as the fault-free patterns. The compressed outputs are then fed into a syndrome counter to derive the signature for the circuit. Simulations were performed on known combinational circuits and the results indicate that the loss in fault coverage caused by compression is in the range of 0-10% which is rather small

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995

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