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A 16-bit×16-bit 1.2 μ CMOS multiplier with low latency vector merging

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3 Author(s)
Amendola, W., Jr. ; Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA ; Srinivas, H.R. ; Parhi, K.K.

This paper presents the VLSI architecture and implementation of a 16×16-bit, bit-level pipelined, two's-complement binary array multiplier. This multiplier architecture employs signed-digit radix 2 carry free adders to perform multiplication. A fast conversion scheme for converting the final product, available from the multiplier array, in radix 2 signed-digit form to two's-complement binary form is employed to reduce the latency of the multiplier, furthermore, it results in savings in area in the form of reduced number or pipelining registers and half adders required for conversion, also called vector merging. This pipelined multiplier uses positive edge triggered registers and employs a single phase clocking scheme. It has been fabricated and tested to perform correctly at 50 MHz clock frequency for a supply voltage of 3.0 V. It may be noted that the speed of this multiplier is limited by 1 binary adder cell time and our test equipment imposed a limit of 50 MHz

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995