A VLSI architecture for the computation of NURBS patches

B-Spline curves and patches are increasingly being used in several areas of computer graphics and geometric modeling. The rationalized counterpart of B-spline called Non-Uniform Rational B-Spline (NURBS) is invariably used in all the present day geometric modeling packages. For an interactive modeling session, thousands of NURBS patches have to be computed and drawn per second. Such performance is beyond the reach of even the most advanced workstations available today. Advances in hardware support for parametric curve and patch generation have thus acquired increased importance. The authors give a complete hardware solution for the generation of NURBS patches.