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Circuit optimization for minimisation of power consumption under delay constraint

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2 Author(s)
Prasad, S.C. ; Inf. Technol. Lab., Texas Instrum. Inc., Dallas, TX, USA ; Roy, K.

We address the problem of optimization of VLSI circuits to minimize power consumption while meeting performance goals. We present a method of estimating power consumption of a basic or complex CMOS gate which takes the internal capacitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. We describe a multipass algorithm which makes use of transistor reordering to optimize performance and power consumption of circuits and which has a linear time complexity per pass. The algorithm has been benchmarked on several large examples and the results are presented

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995

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