Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Partial scan design for technology mapped circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Balakrishnan, A. ; RUTCOR, Rutgers Univ., New Brunswick, NJ, USA ; Chakradhar, S.T.

For a vast majority of production VLSI designs, the synthesis pipeline is interrupted and technology mapping is performed manually. Here, designers map functional specifications directly onto a more richer set of library blocks that include counters and registers. Typically, these blocks have more than one memory element. The scan version of such a block has all flip-flops chained into a shift register during test mode. For such designs, we show that existing partial scan selection methods may produce sub-optimal solutions. We then propose a new method of selecting scan flip-flops in mapped designs. Our algorithm is based on a new formulation that models the presence of multiple memory elements in a library block and also takes into account both area and performance penalties of scan. We also extend a recently proposed integer linear program (ILP) formulation. A graph transformation that was effective in solving the scan selection problem for large synthesized (or unmapped) designs is shown to be inapplicable for mapped designs. We then develop a new transformation that provably preserves optimum solutions for these mapped designs. Experimental results on three production VLSI circuits having 12,000 to over 50,000 gates are reported

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995