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A C-testable modified Booth's array multiplier

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1 Author(s)
Aziz, S.M. ; Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh

In this paper, a C-testable parallel multiplier based on modified Booth's algorithm is presented. The gate-level design requires only 20 vectors to detect all single stuck-at faults. It does not require any extra logic and has no delay overhead compared with the basic non-C-testable design. Five extra inputs are required for the C-testable multiplier, this number can be reached to four using a small amount of extra logic. The multiplier has a regular structure and therefore suitable for use in a silicon compiler

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995