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An HOL based framework for design of correct high level synthesizers

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3 Author(s)
B. M. Subraya ; Dept. of Comput. Sci. & Eng., S.J. Coll. of Eng., Mysore, India ; A. Kumar ; S. Kumar

The paper investigates the problem of designing high level synthesizers which would guarantee correctness of the designs produced. No satisfactory solution to this problem had been available so far. The paper presents a formal framework in which the synthesis and verification processes can be modelled in a practical way. It is shown that the complexity of the verification process can be reduced by following the modularity usually present in a synthesizer design. To simplify the correctness proof of the individual synthesis steps, some easily verifiable templates are defined, in which the algorithms can be expressed. The methodology is embedded in HOL (Higher Order Logic) system

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995