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Transformations for functional verification of synthesized designs

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2 Author(s)
Bradley, W.L. ; Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA ; Vemuri, R.R.

A major problem with low-level functional verification of any hierarchical system is the explosion of reachable states created when clocking mechanisms are incorporated into the model. These additional states make verification more difficult, usually to the point that verification at such a low level is not feasible. Transforms have been developed to take a nonhierarchical model with a complex clocking mechanism and generate a provably equivalent model with a single clock. Furthermore, an algorithm has been developed to take a model with a complex clocking mechanism, described as a hierarchical network of modules, and generate a provably equivalent model with a single clock. These transformed models have a reduced state set and can be verified in place of the original models in a fraction of the original time. This allows a synthesis system to generate simpler verification models, while their results are applicable to the original designs

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995