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Testability-oriented channel routing

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5 Author(s)
Khare, J. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Mitra, S. ; Nag, P.K. ; Maly, W.
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The quality of IC testing can be improved by applying appropriate design strategies. In this paper, we present a testability-oriented routing methodology, which can be used to modify the IC layout so as to reduce the probability of test escape. A testability-oriented iterative channel routing tool based on this methodology has been developed. Example applications of this tool illustrating the methodology are also presented in the paper

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995