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A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology

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4 Author(s)
Puvvada, V. ; Texas Instrum. (India) Pvt. Ltd., Bangalore, India ; Potla, S. ; Selvam, T. ; Suresh, P.R.

The effect of using an n-guardring compared to p-guardring in preventing latchup due to remote transient at drain of I/O buffer n-channel transistor for 0.8 μm CMOS technology is studied. Steady state simulations performed using a 2D device simulator TMA-MEDICI, show that the n-guardring is more effective compared to the p-guardring in increasing the remote trigger level for latchup. It is found that an increase in substrate resistance increased the remote trigger current level for latchup

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995

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