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Wave pipelined architecture folding: a method to achieve low power and low area

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2 Author(s)
D. Ghosh ; SGS-Thomson, New Delhi, India ; S. K. Nandy

Futuristic portable real-time personal communication systems demand low power and high performance simultaneously. This poses a serious challenge to the designers since low power and high performance are two conflicting requirements. In this paper we propose a method called Wave Pipelined Architecture Folding (WPAF) which can be used effectively to reduce power while maintaining the operational throughput. WPAF exploits logic style and architecture along with the clock-free wave pipelining scheme to achieve low power. The technique comes with an additional advantage of reduced chip area which is important from the cost point of view

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995