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An efficient automatic test generation system for path delay faults in combinational circuits

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4 Author(s)
Majhi, A.K. ; Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India ; Jacob, J. ; Patnaik, L.M. ; Agrawal, V.D.

The new test pattern generation system for path delay faults in combinational logic circuits considers robust and nonrobust tests, simultaneously. Once a robust test is obtained for a path with a given transition, another test for the same path with the opposite transition is immediately derived with a small extra effort. To facilitate the simultaneous consideration of robust and nonrobust tests, we derive a new nine-value logic system. An efficient multiple backtrace procedure satisfies test generation objectives. We also use a path selection method which covers all lines in the logic circuit by the longest and the shortest possible paths through them. A fault simulator in the system gives information on robust and nonrobust detection of faults either from a given target set or all path faults. Experimental results on ISCAS'85 and ISCAS'89 benchmark circuits substantiate the efficiency of our algorithm in comparison to other published results

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995