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A fast-multiplier generator for FPGAs

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3 Author(s)
Kumar, S. ; Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia ; Forward, K. ; Palaniswami, M.

FPGA implementation of artificial neural networks calls for multipliers of various word length. In this paper, a new algorithm for generating variable word length multipliers for FPGA implementation is presented. The multipliers generated are based on a Booth Encoded optimized Wallace tree architecture. Several features of FPGA architecture are used to generate fast and efficient multipliers. These multipliers are shown to be 20% faster than existing FPGA multiplier implementations

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995