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Functional test generation for non-scan sequential circuits

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3 Author(s)
M. K. Srinivas ; CAD Lab./SERC, Indian Inst. of Sci., Bangalore, India ; J. Jacob ; V. D. Agrawal

The feasibility of generating high quality functional test vectors for sequential circuits using the Growth (G) and Disappearance (D) fault model has been demonstrated earlier. In this paper we provide a theoretical validation of the G and D fault model by proving the ability of this model to guarantee complete stuck fault coverage in combinational and sequential circuits synthesized employing algebraic transformations. We also provide experimental results on a wide range of synthesized FSMs. A comparison with a state-of-the-art gate level ATPG tool demonstrates the efficiency and limitation of the functional approach

Published in:

VLSI Design, 1995., Proceedings of the 8th International Conference on

Date of Conference:

4-7 Jan 1995