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Ultra low power full adder topologies

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6 Author(s)
Farshad Moradi ; Nanoelectronics Group, Department of Informatics, University of Oslo, NO-0316, NORWAY ; Dag. T. Wisland ; Hamid Mahmoodi ; Snorre Aunet
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In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65 nm standard models are used for simulations.

Published in:

2009 IEEE International Symposium on Circuits and Systems

Date of Conference:

24-27 May 2009