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This paper proposes a novel scheme of self-timed charge recycling search-line (SL) drivers for content-addressable memories. In the conventional charge recycling SL driving scheme , an additional clock needs to be generated from the system clock with stringent requirements for phase and pulse width to control the charge sharing course. In contrast, the proposed scheme can self-sense the end of the charge sharing. Besides, by entering the high-resistant driving state in advance, the proposed scheme reduces the delay overhead of the control logic from 8 to 6 gates delay. Simulation is carried out in a 0.35-mum 3.3-V CMOS process, and the results show the proposed SL driver with load of 512 bits TCAM cells achieves 31.6 fJ/bit/search energy index and 1.19 ns delay time. The achievement illustrates 27.4% energy reduction over buffered driver and 22.2% delay time reduction over the conventional charge recycling SL driver.