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Design of a 64-bit low-energy high-performance adder using dynamic feedthrough logic

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3 Author(s)
Chuang, P. ; Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada ; Li, D. ; Sachdev, M.

In this work, a new design approach in implementing low-energy, high-performance 64-bit adder using dynamic feedthrough logic (DFTL) is introduced and analyzed. Design issues of using DFTL in several logic depth are analyzed in order to achieve the best optimal balance between performance and power consumption. A ldquotiming windowrdquo technique is also proposed to reduce the amount of excessive power dissipation in the DFTL approach. A 64-bit Sklansky carry-merge adder is used as a benchmark comparison between different logic styles including DFTL, CDL, dynamic, and static logic. Simulation results reveal that the proposed work achieves better performance and is more energy efficient than the other logic styles for high performance adder designs.

Published in:

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date of Conference:

24-27 May 2009