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Analysis and design of memoryless interconnect encoding scheme

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3 Author(s)
Ge Chen ; Sch. of Electr. Eng. & Telecommun., Univ. of New South Wales, Sydney, NSW, Australia ; Duvall, S. ; Nooshabadi, S.

Coupling capacitance between adjacent wires in on-chip busses significantly increases the average transition energy dissipation. This paper develops a mathematical model for a memoryless encoding scheme and proposes a novel partitioning method for reducing the transition energy. Specifically, for an 8-bit bus in 65 nm CMOS technology, we present an 11-wire solution that reduces energy dissipation by 22%. The proposed scheme achieves similar energy efficiency without increasing the complexity of the encoding and decoding circuitry when the bus is extended to 16, 32 and 64 bits.

Published in:

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date of Conference:

24-27 May 2009

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