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Efficient test circuit to qualify logic cells

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4 Author(s)
R. P. Ribas ; PGMicro - PPGC / UFRGS, Av. Bento Gonçalves, 9500, Porto Alegre, 91501-970, Brazil ; S. Bavaresco ; M. Lubaszewski ; A. I. Reis

This work proposes a simple, efficient and easy-to-use test circuit for evaluating and validating any set of logic gates in terms of functionality, performance, power consumption and impact in operation of sub-nanometer physical effects.

Published in:

2009 IEEE International Symposium on Circuits and Systems

Date of Conference:

24-27 May 2009