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In this paper, a low-power embedded pseudo-SRAM adopting novel auto-adjusted self-refresh control scheme has been designed. The proposed self-refresh control scheme automatically extends the self-refresh period by monitoring the number of failed cells using error correction code (ECC). The scheme can provide a substantial reduction of data-retention power consumption by choosing an optimal self-refresh period regardless of process, voltage, and temperature (PVT) variations. A 4-Mb embedded pseudo-SRAM designed in a 45-nm embedded DRAM technology providing 1.1-V 166-MHz random cycle operation achieves 57-uW data retention power consumption at room temperature.