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Combined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loops

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2 Author(s)
Tertinek, S. ; Sch. of Electr., Electron. & Mech. Eng., Univ. Coll. Dublin, Dublin, Ireland ; Feely, O.

Recently, several digital phase-locked loops (DPLLs) have been demonstrated to achieve the jitter performance of traditional charge-pump-based analog PLLs. This paper is concerned with a class of DPLLs employing a binary-quantized phase detector, referred to as bang-bang PLLs (BBPLLs). They are widely used in clock and data recovery circuits and have recently been implemented as digital BBPLLs for high-bandwidth synthesis. Given that a DPLL implementation typically suffers from (excess) loop delay, this paper investigates the combined effect of loop delay and reference clock jitter in a first-order digital BBPLL. To statistically characterize the loop's timing jitter we formulate it as a discrete-time vector Markov process and numerically solve the associated Chapman-Kolmogorov equation. This allows us to compute the timing jitter probability density function in steady-state and to evaluate the jitter performance (timing offset and RMS timing jitter) for varying loop detuning, RMS reference clock jitter and loop delay.

Published in:

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date of Conference:

24-27 May 2009