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On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

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4 Author(s)
Ming-Dou Ker ; Dept. of Electron. Eng., I-Shou Univ., Kaohsiung, Taiwan ; Po-Yen Chiu ; Fu-Yi Tsai ; Yeong-Jar Chang

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25degC in the silicon chip. Moreover, it can achieve ESD robustness of over 8 kV in human-body-model (HBM) and 750 V in machine-model (MM) ESD tests, respectively.

Published in:

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date of Conference:

24-27 May 2009