Referenced Items are not available for this document.
High throughput butterfly fat tree (HTBFT) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to butterfly fat tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.
Published in:
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Date of Conference: 24-27 May 2009
- Page(s):
- 2241 - 2244
- E-ISBN :
- 978-1-4244-3828-0
- Print ISBN:
- 978-1-4244-3827-3
- INSPEC Accession Number:
- 10761011
- Conference Location :
- Taipei
- Digital Object Identifier :
- 10.1109/ISCAS.2009.5118244
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
