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High throughput architecture for high performance NoC

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3 Author(s)
Abd El Ghany, M.A. ; Electron. Eng. Dept., German Univ. in Cairo, Cairo, Egypt ; El-Moursy, M.A. ; Ismail, M.

High throughput butterfly fat tree (HTBFT) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to butterfly fat tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.

Published in:

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date of Conference:

24-27 May 2009

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