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A switched capacitor implementation of the generalized linear integrate-and-fire neuron

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8 Author(s)
Folowosele, F. ; Electr. & Comput. Eng. Dept., Johns Hopkins Univ., Baltimore, MD, USA ; Harrison, A. ; Cassidy, A. ; Andreou, A.G.
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In this paper we present the circuits and simulation results for a silicon neuron which is based on a modified version of the Mihalas-Niebur neural model. This silicon neuron produces 15 of the 20 known neural spiking and bursting behaviors. It has low complexity and reliable matching and can thus be easily integrated into more complex neuromorphic systems. Implemented in a 0.15 mum 1.5 V CMOS process, each neuron consumes about 7.5 nW of power at 1 kHz and occupies an area of 70 mum by 70 mum.

Published in:

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date of Conference:

24-27 May 2009