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Embedded a low area 32-bit AES for image encryption/decryption application

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5 Author(s)
Kuo-Huang Chang ; Inst. of Appl. Electron. Technol., Nat. Taiwan Normal Univ., Taiwan ; Yi-Cheng Chen ; Chung-Cheng Hsieh ; Chi-Wu Huang
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Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

Published in:

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date of Conference:

24-27 May 2009

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